The present disclosure relates to the field of communications, and more particularly to automatically detecting multiple electrical devices coupled to an information handling system.
As the value and use of information continues to increase, individuals and businesses seek additional ways to acquire, process and store information. One option available to users is information handling systems. An information handling system (‘IHS’) generally processes, compiles, stores, and/or communicates information or data for business, personal, or other purposes thereby allowing users to take advantage of the value of the information. Because technology and information handling needs and requirements vary between different users or applications, information handling systems may also vary regarding what information is handled, how the information is handled, how much information is processed, stored, or communicated, and how quickly and efficiently the information may be processed, stored, or communicated. The variations in information handling systems allow for information handling systems to be general or configured for a specific user or specific use such as financial transaction processing, airline reservations, enterprise data storage, entertainment, and/or global communications. In addition, information handling systems may include a variety of hardware and software components that may be configured to process, store, and communicate information and may include one or more computer systems, data storage systems, and networking systems.
Many IHS's include a main printed circuit board (also referred to as a motherboard) in which several expansion connectors are coupled to a common communications bus, for example the Peripheral Component Interconnect (PCI) bus and the more recent PCI Express (PCIe) bus. Each expansion connector is capable of receiving an expansion card to provide additional capability to the system. Expansion cards may also be known as add-in-cards (AICs) or simply as cards.
In the PCIe architecture, a root port coupled to a processor/chip set may be coupled to one or more PCIe devices via a PCIe connector. An electrical connection between the root port and the device is a link and each link includes at least one lane (also referred to as channel) with each lane having a set of receiver/transmitter. The PCIe specification presently defines X1, X2, X4, X8, X12, X16, X32 and X64 link widths or lanes, although some of the link widths such as X32 and X64 may be presently unimplemented. The root port and the device negotiate a width of the link during the startup process. Specifically, a basic input output system (BIOS) program detects PCIe devices coupled to PCIe ports during a power on self test (POST) startup phase of the IHS.
Presently, if the width of the root port is greater than the width of the device plugged into the root port, then the unused portion of the width of the root port may not be utilized and thus wasted. That is, if an X4 lane device located on a card is plugged into a root port having X8 lanes, then only X4 lanes of the root port may be utilized. Another X4 lane device located on the same card plugged into the X8 lane root port, and capable of using the remaining X4 lanes, may not be detected and/or may not be trained as a part of the startup process.
Therefore, a need exists for utilizing available bandwidth of a PCIe root port. More specifically, a need exists to develop tools and techniques for detecting multiple independent devices located on a single card that is plugged into a PCIe compliant root port. Accordingly, it would be desirable to provide for detecting and training all devices located on a card plugged into PCIe compliant a root port included in an IHS, absent the disadvantages found in the prior methods discussed above.